1. Field of the Invention
The invention relates to data processing systems and more particularly to addressing apparatus utilizing an improved paging mechanism.
2. Description of the Prior Art
Normally, a computer memory stores both operands and computer commands or instructions. Operands are generally data which are to be operated upon, and commands are instructions which collectively form a computer program. An instruction word normally includes a command portion which addresses a location in the computer memory. The number of locations in memory which can be addressed by a given instruction via binary notation depends on the number of bits allocated to the address portion of the instruction word and the hardware responsive to those bits. Normally, instruction words are comprised of eight-bit bytes, although any other number of bits may be utilized in a byte. Also it is not uncommon for the address portion of an instruction to include one, two, three or more bytes. An address portion of an instruction having only one eight-bit byte can only address 2.sup.8, or 256 locations in memory whereas an address portion having two, eight-bit bytes can address 2.sup.16, or 66,336 locations. Although more memory locations can be addressed with two eight-bit bytes, more time, and a greater number of cycles are necessary in fetching each address word from memory. Furthermore, more memory space is necessary in storing the larger words. With the trend toward minicomputers and microprocessors, computer memory and throughput is at a premium. Accordingly, what is required for minicomputers, microprocessors and communication processors, is an improved addressing mechanism which will permit greater addressing capability with a minimum of computer cycle time in fetching the address portion of an instruction.
The prior art is replete with memory addressing devices which have been designed to improve the addressing of computer main memories. A typical computer main memory addressing mechanism is shown in U.S. Pat. No. 3,267,462. This is a straightforward addressing mechanism with the ability to address any desired number of characters beginning with any randomly selected position.
Instructions stored in main memory, are generally stored in contiguous locations in groups so that the group comprises a computer program. Accordingly, it is generally not necessary to fetch another address to locate the second instruction and so on, because the original address can be modified by adding the number one (or some other number) to the address already fetched to acquire the next contiguous location to be fetched.
Other modification techniques comprise index-registers which are addressed by the original address and either replace or modify the original address to give a new address for the operand to be fetched. A typical device of this type is disclosed by H. Trauboth in U.S. Pat. No. 3,284,778 issued Nov. 8, 1966.
Further refinements to the computer addressing techniques led to relative addressing wherein the address portion of an instruction does not refer to the absolute memory address desired but to some address relative to a page or segment located in main memory. Accordingly, hardware can concatenate the relative address within a segment or page with the location of the beginning of that segment or page within main memory to locate the absolute address. Typical of this type of apparatus is the U.S. Pat. No. 3,938,096 to James L. Brown, et al issued Feb. 10, 1976, and U.S. Pat. No. 3,461,433 issued to W. C. Emerson on Aug. 12, 1969.
Still other addressing schemes increase speed and throughput by making use of a high-speed, small capacity memory to the main memory, and to which addresses are fetched prior to their use by the addressing mechanism. Hence speed in addressing is attained. Typical of this type device is that disclosed by Yohan Chu in U.S. Pat. No. 3,251,041 issued May 10, 1966.
To increase main memory capacity, a virtual memory system was devised wherein the operating system, such as that used in the IBM System 370, maps addresses resident on magnetic disk on to main memory. The user addresses main memory and the appearance to the user is that he has a vast capacity of main memory. (See Computer Organization and the System/370 by Harry Katzan Jr., published in 1971 by Van Nostrand Reinhold Company of New York). This is some of the prior art relating to memory addressing schemes of which the applicants are aware. It is presented as background information and no implication should be drawn that this is the closest prior art to the invention or that a search has been made.
All these schemes have generally been directed to large computer systems and generally require additional hardware such as index registers, buffer-memories. Moreover, memory space is not as much at a premium for large computers as with small computers.
What is required of the small computer is an improved address modification system which uses the hardware of the basic addressing mechanism and at the same time minimizes cycle time for accessing multiple address words.